As is known in the art, photolithography is used extensively in the fabrication of a wide variety of semiconductor structures. One type of semiconductor structure has active devices, such as field effect transistors (FETs), formed in active semiconductor regions (sometimes referred to as the active regions) of a substrate. More particularly, a plurality of active semiconductor devices is formed in a semiconductor region, typically a semiconductor epitaxial layer, formed over the substrate. A gate electrode controls a flow of carriers passing through the active semiconductor region between a source electrode and a drain electrode. More particularly, the active semiconductor region has a pair of source and drain electrodes in ohmic contact with the active semiconductor region and a gate electrode in Schottky contact with the source and drain region. The gate electrode is a control electrode for controlling a flow of carriers through the active semiconductor region between the source and drain electrodes.
One technique used to isolate the active devices is to etch away boundary portions of the semiconductor active region down to an insulating layer to thereby leave isolated semiconductor mesas with each active device being formed in a corresponding one of the mesas. Another technique uses ion implantation around the boundary portions of the semiconductor active regions to render the boundary regions inactive (i.e., into a non-semiconductor, insulating region) to isolate the active devices. The region in the active semiconductor region under the gate electrode and through which the carriers flow is sometimes referred to as the gate channel. The region of the active semiconductor region between the source and drain electrodes is sometimes referred to as the source-drain (SD) channel. The length of the gate electrode is the dimension of the gate electrode measured along a direction passing through the source and drain electrodes and is referred to as the gate length.
One process used to form such FET is to first form source and drain contacts in ohmic contact with the surface of the active semiconductor region as shown in (FIG. 1A) and then cover the entire semiconductor surface including the source (S) and drain (D) contacts, with a dielectric layer, as shown in FIG. 2A. Next, a photoresist layer is deposited over the entire dielectric layer (both the portion of the dielectric layer on the active semiconductor region and the portion of the dielectric layer adjacent to the semiconductor active region, as shown in FIGS. 1B-1D and 2B. More particularly, the elevation of the tops of the source and drain contacts above the surface of the substrate creates topography height variations in the photoresist layer (i.e., the above-described “pools”) at the two ends of semiconductor active regions lying between the two ohmic contact metals used for the source and drain contacts. This topography height variation causes the above-described pooling. It is noted that this pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed.
After the photoresist layer deposition, a binary mask, not shown, is placed over the photoresist layer. Next, the masked photoresist layer is exposed to ultraviolet light, and then developed to form a window in the photoresist layer over portions of the dielectric layer disposed over the gate formation region on the active semiconductor region, FIG. 2C. Next, the windowed photoresist layer is exposed to an etchant to remove the exposed dielectric layer and thereby expose the region of the active semiconductor region where the gate electrode is to be contact therewith, FIG. 2D. Next, the gate electrode is to be formed in Schottky contact with the exposed region of the active semiconductor region. Unfortunately, because of the change in the surface topology over which the photoresist layer is deposited, for example over the source and drain contacts, portions of the above-described pooling of the photoresist are created on the outer portions of the source and drain contacts and on the region where the gate electrode is to make Schottky contact with the underlying portion of the active semiconductor region (i.e., the source drain (SD) channel). That is, the pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed.
This pooling causes the photoresist to be thicker than the desired thickness on the active semiconductor region and, after the photoresist is developed, results in a failure of that portion of the gate electrode to make contact with the underlying portion of the active semiconductor region but rather terminates on the silicon nitride dielectric layer as shown in FIGS. 2 and 2E. The failure to make contact with the underlying portion of the active semiconductor region results in a “pinched characteristic”, the gate fails to make Schottky contact with the active semiconductor region.
This has been addressed in the e-beam process by adding a patch feature to allow additional exposure in this region; however when less expensive optical lithography is used to pattern the photoresist layer, a patch feature requires either an additional mask and exposure step using a sub resolution patch feature, or a patch made by increasing the size of the gate in the region where the resist is thicker so that additional exposure energy can be transferred to this region. When using optical lithography without one of these patch features, an increase in the exposure dose of the ultraviolet light would be required to clear the pooling region in photoresist layer near the edge of the SD channel and thereby prevent “pinched gates”. This would however result in an increase in gate channel length in the region of the active semiconductor region where there is this increased exposure and thus would limit the minimum critical dimension (CD) (i.e., the gate channel length) that can be achieved with a binary mask and this increase of the gate channel length in the active region of the device can cause poor electrical performance.
In accordance with the present disclosure, a semiconductor structure is provided having: a substrate having an inactive region and an adjacent active semiconductor region; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, between a pair of electrical contacts on the surface of the substrate; and a photolithographic, thickness non-uniformity, compensation feature, on the inactive region.
The inventors have recognized that making the pooling occur in regions off the active semiconductor region (i.e., on the inactive region) removes the requirement of using the increase in the exposure dose of the ultraviolet light on the active semiconductor region where the gate is to be formed. The non-uniformity, compensation feature shifts the pooling from regions on the active semiconductor region to regions off the active semiconductor region. More particularly, the photoresist layer is deposited with a proper thickness on the non-pad regions of the substrate so that this proper thickness will be on the portions of the active semiconductor region where the gate electrode will be formed.
In one embodiment, the non-uniformity, compensation feature includes pads, the pads being at substantially the same elevation as the tops of the electrical contacts, and elevating the photoresist in regions off of the active region (i.e., the elevated regions causing the pooling). This elevated photoresist then continues over the active semiconductor region at substantially the same elevation as the tops of the electrical contacts while being at the proper elevation over the active semiconductor region where the gate electrode is to be formed (i.e., the non-electrical contact regions). Further such shifting of the position of the pooling to regions off the semiconductor active regions enables the use of gate formation compensation such as enlarging the gate opening in the gate mask to allow more energy to be delivered to the region of thicker resist with any increase in gate length resulting from this larger section occurring in a region which does not impact device performance (i.e., off of the active semiconductor region).
In one embodiment, the pads are on the inactive region.
In one embodiment, the feature comprises two pair of pads on opposite sides of the active semiconductor region.
In one embodiment, the pads in each pair of the pads are disposed along parallel lines displaced from a line passing through the control electrode.
In one embodiment, the compensation feature comprises a region in the control electrode on the inactive region that is wider than a region of the control electrode on the active semiconductor region and narrower than the contact pad for the control electrode. The width of the region in the control electrode is selected to increase the relative intensity of ultraviolet light transmitted such that the thicker resist in the region of the gate electrode is sufficiently exposed.
In one embodiment, a method is provided for forming a semiconductor structure, such structure having: a substrate having an active semiconductor region and an adjacent inactive region; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts. The method includes: forming a photoresist layer over the pair of contacts prior to formation of the gate electrode; and providing a photolithographic, thickness non-uniformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate on the inactive region for preventing pooling of the photoresist layer on the active semiconducting region.
In one embodiment, the feature forming includes forming pads on the inactive region.
In one embodiment, a semiconductor structure is provided comprising: a substrate; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrode, the control electrode extending from the active semiconductor region to a contact pad on the inactive region and wherein a portion of the control electrode between the active semiconductor region and the contact pad is wider than a portion of the control electrode on the active semiconductor region.
In one embodiment, a semiconductor structure is provided, comprising: a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of additional electrodes on the active semiconductor region, the control electrode extending from the active semiconductor region to a region on the substrate off of the active semiconductor region; a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads.
The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims.
Like reference symbols in the various drawings indicate like elements.